1. Field of the Invention
The invention generally relates to a semiconductor storing device, and more particularly to a redundancy of a NAND Flash Memory.
2. Description of Related Art
In semiconductor memories such as NAND flash memory, dynamic random access memory or the likes, the integrity thereof increases year by year. As a result, it is difficult to manufacture storing elements without flaws and defects. Therefore, a redundancy method which compensates the physical defects in appearance of the storing elements generated during manufacturing process has been adapted on a storing chip. For example, in some redundancy methods, an address conversion circuit and a redundancy memory area are included. The address conversion circuit converts the address of the storing elements having physical defects to an address of the storing elements of a redundancy storing area, and the redundancy storing area is configured to compensate for the storing elements having defects. The address information of the storing elements having defects and the storing elements of the redundancy storing area are stored in fuse read only memory, register, or the like during memory chip testing or at the completion of the fabrication. In addition, if the address of the storing elements having defects is being inputted and the address is being detected, the storing elements having defects would be forbidden to access. Instead, the storing elements of the redundancy storing area is being accessed such that it appears to be a storing elements without any defects from the appearance (for example, patent documents 1 and 2). By such redundancy method, even if a small amount of storing elements yield defects, they can still be treated as qualified product. As such, the yield can be increased while the manufacturing cost of the memory can be reduced.
Furthermore, in semiconductor memories, other than utilizing redundancy to compensate for physical defect elements, an error detection and correction circuit has been disposed internally as well to serve as a soft error countermeasures, thereby increasing the reliability.
[Patent Document 1] Japanese Patent No. 2000-311496
[Patent Document 2] Japanese Patent No. 2002-288993
Accordingly, the storing elements having redundancy function or an ECC circuit are being equipped in the semiconductor memories such as NAND flash memory or the like to compensate for the defects in storing elements. FIG. 1 is a schematic diagram illustrating the redundancy of the flash memory and error correction. A main storing area MM and a redundancy storing area MR thereof are configured in a storing array 400 of the NAND flash memory. If a page is being read from the storing array 400, a page of data would be transmitted to a page buffer/sensing circuit 410. The data would be sensed by the sensing circuit, and the data sensed would be retained in a data register 412.
A page of the main storing area MM and the redundancy storing area MR is, for example, 2000 bytes. While reading the page, for example, a half (i.e. 1000 bytes) of the even bit data is transmitted to a data register DR-0, and the remaining half (i.e. 1000 bytes) of the odd bit data is transmitted to a data register DR-1. Alternatively, the data located physically on the left of the main storing area MM is transmitted to the data register DR-0, and the data located on the right is transmitted to data register DR-1.
Herein, in the present specification, the storing elements having physical defects is called “defect elements,” the data stored in the defect elements are called “defect data,” the row bits of the defect element is called “defect bits,” the storing elements of the redundancy storing area is called “redundancy element,” the data stored in the redundancy element is called “redundancy data,” and the row bits of the redundancy element is called “redundancy bits.” In addition, the storing elements are synonymous with memory cell.
The redundancy storing area MR is, for example, M bits, and the redundancy storing area MR is constituted by allocating half of the bits (i.e. M/2 bits) to the data register DR-0 and M/2 bits to the data register DR-1. For example, the even redundancy bit data of the redundancy storing area MR is transmitted to the data register DR-0, and the odd redundancy bit data is transmitted to the data register DR-1.
The page buffer 410 also includes a cache register 414 which retains the data parallel transmitted from the data register 412. The cache register 414 includes cache registers CR-0 and CR-1. The cache register CR-0 receives data transmitted from the data register DR-0 through a transmission transistor (not illustrated). The cache register CR-1 also retain the data transmitted from the data register DR-1. The data retained in the cache register CR-0 includes the data coming from the main storing area MM (hereinafter core data) and the redundancy data coming from the redundancy storing area MR. The data retained in the cache register CR-1 also includes the core data and the redundancy data.
A row selecting circuit 420 includes transform circuits 422-0 and 422-1 adapted for replacing the core data retaining in the cache registers CR-0 and CR-1 with the redundancy data. The data retained in the cache registers CR-0 and CR-1 is being corrected or inputted/outputted is done by transmitting the data to the transform circuits 422-0 and 422-1 through the transmission transistor (not illustrated).
Redundancy data such as the row address of the defect bits or the row address of the redundancy bits which replaces the row address of the defect bits are stored by fuse ROM or other nonvolatile media. The transform circuit 422-0 transforms the defect data included in the core data of the cache register CR-0 into the redundancy data according to redundancy information. Similarly, the transform circuit 422-1 transforms the defect data included in the core data of the cache register CR-1 into the redundancy data.
The data transformed by the transform circuits 422-0 and 422-1 is outputted to an ECC circuit 430. The data corrected by the ECC circuit 430 is recovered as the core data and the redundancy data through the transform circuits 422-0 and 422-1. The corrected core and redundancy data are respectively written back to the cache registers CR-0 and CR-1.
The corrected core and redundancy data retained in the cache registers CR-0 and CR-1 are outputted to an I/O buffer 440 after transformed by the transform circuits 422-0 and 422-1. The operation of the cache registers CR-0, CR-1, the ECC circuit 430, and the I/O buffer 440 are performed alternately by the following method. During a period in which the corrected data of the cache register CR-0 is outputted to the I/O buffer 440, the ECC circuit 430 is utilized to correct the error in the data of the cache register CR-1. During a period in which the corrected data of the cache register CR-1 is outputted to the I/O buffer 440, the ECC circuit 430 is utilized to correct the error in the data of the cache register CR-0.
In the foregoing redundancy method, since halves of the redundancy storing area MR are equally allocated such that half of the redundancy bits is allocated for ½ page of core data, even assuming the total defect bits in one page is less or equal to M bits, the defect bits cannot be compensated under the circumstances such that the defect bits exist in ½ page of core data is over M/2 bits. For example, defects in metal contact usually occurs in local regions, and as a result, sometimes the core data of one of the data registers DR-0 would include more defect bits while another data register DR-1 does not include defect bits. Therefore, when evenly allocate the redundancy bits of the redundancy storing area MR to ½ page of core data, the efficiency of the compensation using redundancy data would decrease, thereby fail to increase the yield rate of the chips.
Furthermore, the data corrected by the ECC circuit 430 is re-written to the cache registers CR-0, CR-1 through the row selecting circuit 420, and when the data is being outputted to the I/O buffer 440, the defect bits of the core data are transformed into the redundancy bits through the transform circuits 422-0 and 422-1 again. Therefore, when the cache registers CR-0 and CR-1 are outputting data, it is necessary to pass the transform circuits 422-0 and 422-1. As a result, the cache operation speed is hindered.